High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2021-06, Vol.68 (6), p.2457-2469
• Main Authors: Zhou, Jie, Qian, Huizhen Jenny, Luo, Xun
• Format: Article
• Language: English
• Subjects: Amplification; Amplitudes; Broadband; Calibration; CMOS; Digital to analog converters; Error compensation; High resolution; Linearity; low amplitude/phase error; Phase error; phase linearity enhancement; Phase shifter; Phase shifters; Power consumption; PVT-insensitive; Quadratures; Signal generation; System-on-chip; Topology; Variable gain; Voltage control; Wideband
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2021.3063274

In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360° range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22-44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36-0.59 dB and RMS phase error of 0.92° −1.02° without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage.