Design and implementation of coupler-based Ka-band CMOS power splitters

• Published in: Analog integrated circuits and signal processing 2021-07, Vol.108 (1), p.25-36
• Main Authors: Lin, Yo-Sheng, Yeh, Bing-Ting, Lan, Kai-Siang
• Format: Article
• Language: English
• Subjects: Circuits and Systems; CMOS; Couplers; Electrical Engineering; Engineering; Extremely high frequencies; Millimeter waves; Power dividers; Power splitters; Signal,Image and Speech Processing; Transceivers; Transmission lines; Wave power
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-021-01801-6

We propose a novel power splitter (or divider) comprising two back-to-back quarter-wavelength (λ/4) coupled lines (i.e. coupler). To improve the isolation between the output ports (i.e. ports 2 and 3), an isolation resistor R is included. Three power dividers are designed and implemented. To enhance the reflection coefficients, and S 21 and S 31 and their amplitude imbalance (AI) and phase difference (PD), the output ports transmission lines (TLs) of the first power divider (i.e. divider-1) with R of 100 Ω adopt tapered width from 8 to 3 μm. For contrast, the second power divider (i.e. divider-2) with R of 100 Ω uses tapered width from 8 to 3 μm for the input port (i.e. port 1) TL. To study the effect of R on the performance of the power divider, the third power divider (i.e. divider-3) has the same layout with divider-2 except R equal to 50 Ω. Prominent results are obtained. For instance, divider-1 occupies a small chip area of 0.026 mm 2 (i.e. 2.3 × 10 −4 λ 0 2 ), one of the smallest normalized chip areas ever reported for millimeter-wave power dividers. Moreover, at 33 GHz, divider-1 achieves excellent S 11 of − 13.1 dB, S 22 of − 14 dB, S 33 of − 14.2 dB, and S 32 of − 17.9 dB, S 21 of − 4.22 dB, S 31 of − 3.99 dB, AI of − 0.23 dB, and PD of 2.1°. The remarkable results of the proposed power divider structure indicate that it is suitable for Ka-band and even higher frequency transceivers.