An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its le...

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Bibliographic Details
Published in:Electronics (Basel) 2021-06, Vol.10 (11), p.1328
Main Authors: Park, Jungwoo, Kim, Soontae, Hou, Jong-Uk
Format: Article
Language:English
Subjects:
Computer architecture
Data integrity
Energy consumption
Power consumption
Simulators
Smartphones
Transistors
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Summary:Conventional 2-level cache architecture is not efficient in mobile systems when small programs that do not require the large L2 cache run. Bypassing the L2 cache for those small programs has two benefits. When only a single program runs, bypassing the L2 cache allows to power it down removing its leakage energy consumption. When multiple programs run simultaneously on multiple cores, small programs bypass the L2 cache while large programs use it. This decreases conflicts in the L2 cache among those programs increasing overall performance. From our experiments using cycle-accurate performance and energy simulators, our proposed L2 cache architecture supporting bypassing is shown to be effective in reducing L2 cache energy consumption and increasing overall performance of programs.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics10111328