A Compressive Sensing CMOS Image Sensor With Partition Sampling Technique

A CMOS image sensor (CIS) that performs compressive sensing (CS) image encoding without compromising the operating speed and hardware complexity is presented in this article. The conversion rate and the frame rate of the sensor are increased by using a high-order sigma-delta (ΣΔ) analog-to-digital c...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 2021-09, Vol.68 (9), p.8874-8884
Main Authors: Lee, Hyunkeun, Kim, Woo-Tae, Kim, Jinho, Chu, Myonglae, Lee, Byung-Geun
Format: Article
Language:English
Subjects:
Analog to digital conversion
Analog to digital converters
Analog-digital conversion
Analog-to-digital converter (ADC)
CMOS
CMOS image sensor (CIS)
CMOS image sensors
Compressed sensing
compressive/compressed sensing
Distortion
Figure of merit
Hardware
high-order sigma-delta (ΣΔ) modulator
Image coding
image processing
Image reconstruction
Power consumption
Sampling methods
Sampling techniques
Sensors
set partitioning problem
Weighting functions
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A CMOS image sensor (CIS) that performs compressive sensing (CS) image encoding without compromising the operating speed and hardware complexity is presented in this article. The conversion rate and the frame rate of the sensor are increased by using a high-order sigma-delta (ΣΔ) analog-to-digital converter (ADC) to obtain linear measurements of selected pixel values for CS encoding. Image distortion caused by the nonconstant weight function of high-order ΣΔ ADCs is eliminated by using the proposed sampling technique. The sampling technique makes the effective weights of the inputs to the ADC equal by applying a solution for the set partition problem. In addition, unlike the existing block-based CS encoding scheme that requires complicated analog multiplexers, the proposed column-based CS encoding scheme can be implemented in a hardware-efficient column-parallel fashion, as in conventional CISs. The CIS is fabricated in a 0.11-μm 1P4M CIS process, and the sampling technique and encoding scheme are successfully demonstrated. It achieves a readout noise of 2.63 e - rms and a dynamic range of 67.96 dB with a power consumption of 56.38 mW. The resulting figure of merit is 0.375 e - ·nJ, which is the lowest among those of recently reported state-of-the-art CS-CISs.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2020.3018053