Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2021-07, Vol.68 (7), p.3513-3519
Main Authors: Pei, Zhenlin, Dutta, Arin, Shang, Liuting, Jung, Sungyong, Pan, Chenyun
Format: Article
Language:English
Subjects:
Antiballistic materials
Ballistic material
channel density
Co-design
Contact resistance
Delays
Design optimization
design/technology co-optimization
Graphene
Integrated circuit interconnections
Integrated circuits
interconnect
Interconnections
mean free path (MFP)
Power management
Quantum capacitance
Resistance
Wires
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Summary:Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this article, an interconnect technology/system codesign methodology is presented to efficiently optimize generic interconnects using ballistic materials. The key requirements of material-level characteristics to replace conventional Cu counterparts are quantified, such as the channel density, mean free path (MFP), and contact resistance. Furthermore, to achieve maximal chip-level throughput, two interconnect design schemes are proposed and optimized under a given number of metal layers, die area, and power density constraints. Results demonstrate that the optimal design scheme strongly depends on the power constraint, driving devices as well as material parameters, including the contact resistance. It is shown that up to 45% of the throughput improvement can be achieved by replacing both local and intermediate Cu interconnects at an ultralow-power budget.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3077210