Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations

• Published in: IEEE journal of solid-state circuits 2021-07, Vol.56 (7), p.2245-2255
• Main Authors: Ryu, Sungju, Koo, Jongeun, Kim, Wook, Kim, Yonghwan, Kim, Jae-Joon
• Format: Article
• Language: English
• Subjects: Clocks; CMOS; Critical path; Delays; Digital systems; Elastic clock; Electric potential; Encryption; Energy consumption; Error correction; Image edge detection; Logic gates; low-voltage operation; Pipelines; Timing; timing error correction; timing margin; variation tolerance; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2020.3048881

We introduce a new clocking approach for digital systems to achieve better resilience to process, voltage, and temperature (PVT) variations. The proposed scheme is based on elastic clock methodology that uses locally generated clocks and elastic handshaking control, thereby achieving efficient and fast adaptation to the variations. However, the elastic clock-based design still requires a significant amount of timing margins due to delay mismatch between the critical path and the replica path for local clock generation, thus reducing the advantages of the elastic clock. We propose a timing error correction scheme tailored to the elastic clock methodology to eliminate such an extra timing margin. We implement an encryption/decryption core in 28-nm CMOS technology for silicon verification. Measurement results show that the proposed scheme reduces energy consumption by 35% and achieves 3.86 \times higher performance over the margined baseline design.