An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and w...

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Bibliographic Details
Published in:Electronics (Basel) 2019-01, Vol.8 (1), p.13
Main Authors: Ramkaj, Athanasios, Strackx, Maarten, Steyaert, Michiel, Tavernier, Filip
Format: Article
Language:English
Subjects:
Accuracy
Analog to digital conversion
Analog to digital converters
Calibration
CMOS
Critical path
Design
Noise measurement
Self calibration
Simulation
Topology
Transistors
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Summary:This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics8010013