Design, Implementation and Evaluation of a Low Redundant Error Correction Code

The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (E...

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Bibliographic Details
Published in:Revista IEEE América Latina 2021-11, Vol.19 (11), p.1903-1911
Main Authors: Gracia-Moran, Joaquin, Saiz Adalid, Luis J., Baraza Calvo, Juan Carlos, Gil Tomas, Daniel, Gil Vicente, Pedro J.
Format: Article
Language:English
Subjects:
Circuits
CMOS
Coders
Decoding
Delay
Error correction
Error correction & detection
Error Correction Code
Error correction codes
Fault-Tolerant Systems
Irrigation
Low Redundancy
Microprocessors
Multiple Cell Upsets
Power consumption
Reduced instruction set computing
Redundancy
Reliability
Signal to noise ratio
Silicon
Silicon compounds
Single Cell Upsets
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Summary:The continuous raise in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, computer memory is affected by Single Cell Upsets (SCU) and Multiple Cell Upsets (MCU). A common method to tolerate errors in this element is the use of Error Correction Codes (ECC). The addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to allow detecting and/or correcting errors. ECC can be designed with different parameters in mind: low redundancy, low delay, error coverage, etc. The idea of this paper is to study the effects produced when adding an ECC to a microprocessor with respect to overheads. Usually, ECC with different characteristics are continuously proposed. However, a great quantity of these proposals only present the ECC, not showing its behavior when using them in a microprocessor. In this work, we present the design of an ECC whose main characteristic is a low number of code bits (low redundancy). Then, we study the overhead this ECC introduces. Firstly, we show a study of silicon area, delay and power consumption of encoder and decoder circuits, and secondly, how the addition of this ECC affects to a RISC microprocessor.
ISSN:1548-0992
1548-0992
DOI:10.1109/TLA.2021.9475624