High-Performance Carry Select Adders

This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based S...

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Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2021-08, Vol.40 (8), p.4169-4185
Main Authors: Jothin, R., Sreelatha, P., Ahilan, A., Mohamed, M. Peer
Format: Article
Language:English
Subjects:
Adding circuits
Circuits and Systems
Converters
Design optimization
Electrical Engineering
Electronics and Microelectronics
Energy conversion efficiency
Energy efficiency
Engineering
Instrumentation
Power consumption
Short Paper
Signal,Image and Speech Processing
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Summary:This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a new logic optimization on the carry propagation path to improve speed of operation, area and energy efficiency. The second proposed method is an optimized design of the regular SQRT CSLA by employing the carry enable and add-one ripple carry adder (ARCA) architectures to decrease the number of gates. Simulation results show that the proposed CEBEC SQRT CSLA offers a savings of 22.81%, 9.95%, 7.95% and 3.98% on area, 14.50%, 5.21%, 3.72% and 3.11% in power consumption and offers 6.78%, 15.46%, 6.57% and 3.83% lesser delay, 20.33%, 19.92%, 10.09% and 6.89% lesser PDP, 28%, 23.85%, 13.78% and 7.58% lesser ADP than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures. The proposed ARCA SQRT CSLA architecture exhibits 9.26%, 17.71%, 9.06% and 6.39% lesser delay than the existing regular, BEC SQRT CSLA, SQRT CSLA1 and SQRT CSLA2 architectures.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-021-01658-0