3-D AND-Type Flash Memory Architecture With High-κ Gate Dielectric for High-Density Synaptic Devices

• Published in: IEEE transactions on electron devices 2021-08, Vol.68 (8), p.3801-3806
• Main Authors: Seo, Young-Tak, Kwon, Dongseok, Noh, Yoohyun, Lee, Soochang, Park, Min-Kyu, Woo, Sung Yun, Park, Byung-Gook, Lee, Jong-Ho
• Format: Article
• Language: English
• Subjects: 3-D stackable flash memory; AND-type flash; Arrays; Artificial neural networks; CIFAR-10; Computer architecture; convolutional neural network (CNN); Density; Flash memory (computers); Hardware; Image classification; Logic gates; Microprocessors; Multilayers; neuromorphic; Neuromorphics; Performance evaluation; Silicon; Stacking; synapse array; Synapses; synaptic device
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2021.3089450

Advanced 3-D synaptic devices with a stackable AND-type rounded dual channel (RDC) flash memory structure are proposed for neuromorphic networks. AND synaptic arrays composed of RDC flash devices enable program/erase (PGM/ERS) using Fowler-Nordheim (FN) tunneling, high-speed operation because of parallel read operations, and high density with multilayer stacking. Key fabrication steps are explained and the successful operation of the device in 3-D stacked structure is verified by measurement results. In addition, current summation and selective PGM/ERS behavior in synaptic arrays, which are essential in neuromorphic networks, are demonstrated. A hardware-based convolutional neural network (CNN) is designed considering the operating characteristics of the RDC flash memory. The accuracy evaluation and analysis for the CIFAR-10 image classification are performed. In addition, we propose a method of constructing a hardware-based CNN with the high-density synaptic array by stacking layers.