System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2021-09, Vol.68 (9), p.4242-4250
Main Authors: Kranthi, N. K., Sarro, James Di, Sankaralingam, Rajkumar, Boselli, Gianluca, Shrivastava, Mayank
Format: Article
Language:English
Subjects:
Chokes
Computer architecture
Current filaments
drain-extended nMOS [laterally double diffused MOS (LDMOS)]
electrostatic discharge (ESD)
Electrostatic discharges
Failure
Failure mechanisms
High voltages
IEC
Inductors
Integrated circuits
International Electrotechnical Commission (IEC)
Metal oxide semiconductors
Pins
Pulse shape
Shape
Silicon controlled rectifiers
Stress
system-level ESD
Temperature measurement
Waveforms
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Summary:A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3100810