ASIC implementation of Up-sampling Built in 6GS/s-16bit DAC

This paper presents an interpolation filtering model including four Digital interpolation filters. The interpolation filter circuit can effectively increase the data rate without increasing the input rate of the interface, and realize the up-sampling processing of the external input low-frequency di...

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Bibliographic Details
Published in:Journal of physics. Conference series 2019-11, Vol.1345 (2), p.22015
Main Authors: Zhu, Zehua, Quan, Haiyang, Wang, Zongmin, Zhang, Tieliang, Peng, Xinmang
Format: Article
Language:English
Subjects:
Circuits
Interpolation
Physics
Sampling
Signal processing
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Online Access:Get full text
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Description
Summary:This paper presents an interpolation filtering model including four Digital interpolation filters. The interpolation filter circuit can effectively increase the data rate without increasing the input rate of the interface, and realize the up-sampling processing of the external input low-frequency digital signal to meet the high-speed DAC core conversion data requirement.
ISSN:1742-6588
1742-6596
DOI:10.1088/1742-6596/1345/2/022015