Loading…

The TaichuPix1: a monolithic active pixel sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these...

Full description

Saved in:
Bibliographic Details
Published in:Journal of instrumentation 2021-09, Vol.16 (9), p.P09020
Main Authors: Wu, T., Wei, W., Grinstein, S., Casanova, R., Zhang, Y., Wei, X., Dong, J., Zhang, L., Li, X., Liang, Z., Guimaraes da Costa, J., Lu, W., Li, L., Wang, J., Zheng, R., Yang, P., Huang, G.
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection mechanism using a radioactive source. These results prove that the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify that it can work up to about 3 Gbps, while they also indicate that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/16/09/P09020