Electrical characterization of MOS structures with self-organized three-layer gate dielectric containing Si nanocrystals

SiOx (x 1.3) films with thicknesses of 50 and 100 nm deposited on c-Si by thermal evaporation of SiO in vacuum were subjected to N2 or two steps N2, 90%N2+10%O2 annealing at 1000 oC for 60 min. The time of the second (N2+10%O2) annealing step was varied in order to vary the depth to which the SiOx f...

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Bibliographic Details
Published in:Journal of physics. Conference series 2010-11, Vol.253 (1), p.012034
Main Authors: Nedev, N, Nesheva, D, Curiel, M, Manolov, E, Petrov, I, Valdez, B, Bineva, I
Format: Article
Language:English
Subjects:
Annealing
Diameters
Dielectrics
Electrical properties
Nanocrystals
Physics
Silicon dioxide
Thickness
Vacuum thermal evaporation
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Summary:SiOx (x 1.3) films with thicknesses of 50 and 100 nm deposited on c-Si by thermal evaporation of SiO in vacuum were subjected to N2 or two steps N2, 90%N2+10%O2 annealing at 1000 oC for 60 min. The time of the second (N2+10%O2) annealing step was varied in order to vary the depth to which the SiOx films were intentionally oxidized. The I–V and XTEM results obtained confirm that the suggested two steps annealing leads to a formation of three-layer SiO2/SiO2-Si nanocrystals/SiO2 gate dielectric, which contains Si nanocrystals. The nanocrystals are with a diameter of a ∼ 4-5 nm and are embedded in a stoichiometric SiO2 matrix. The I–V measurement show that the current through the gate dielectric is limited by a SiO2 region, close to the top surface, formed during the second annealing step. MOS structures subjected to a two step annealing show larger retention times when charged with electrons/holes in comparison with the control or annealed only in N2 structures.
ISSN:1742-6596
1742-6588
1742-6596
DOI:10.1088/1742-6596/253/1/012034