Interleaved Planar Packaging Method of Multichip SiC Power Module for Thermal and Electrical Performance Improvement

• Published in: IEEE transactions on power electronics 2022-02, Vol.37 (2), p.1615-1629
• Main Authors: Yang, Fengtao, Lixin, Jia, Wang, Laili, Zhang, Fan, Wang, Binyu, Zhao, Cheng, Wang, Jianpeng, Bayer, Christoph, Ferreira, Jan
• Format: Article
• Language: English
• Subjects: Commutators; Cooling; Current sharing; Decoupling; Electronic devices; Electronic packaging thermal management; Inductance; Modules; MOSFET; Multichip modules; Multichip power module; Packaging; parallel MOSFETs; Silicon carbide; Substrates; Switches; Thermal coupling; Thermal resistance
• ISSN: 0885-8993; 1941-0107
• DOI: 10.1109/TPEL.2021.3106316

Double-sided cooling based on planar packaging method features better thermal performance than traditional single-sided cooling based on wire bonds. However, this method still faces thermal and electrical challenges in multichip SiC power modules. Specifically, one is severe thermal coupling among parallel bare dies, and the other is unbalanced current sharing due to unreasonable layout design. This article aims to explore the potentials of SiC power devices in power module, which are higher current capability and reliability. The proposed packaging method is called interleaved planar packaging and can get rid of the optimizing contradiction between thermal and electrical performance. In this packaging method, there are two functional units: interleaved switch unit and current commutator structure. Benefited from the two units' electromagnetic and thermal decoupling effects, the interleaved power module features low loop inductance, balanced current, low coupling thermal resistance, and even thermal distributions. A 1200 V 3.25 mΩ half-bridge SiC power module based on interleaved planar packaging is fabricated and tested to verify this method's superiority.