Comparing controlled system synthesis and suppression enforcement

Runtime enforcement and control system synthesis are two verification techniques that automate the process of transforming an erroneous system into a valid one. As both techniques can modify the behaviour of a system to prevent erroneous executions, they are both ideal for ensuring safety. In this p...

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Bibliographic Details
Published in:International journal on software tools for technology transfer 2021-08, Vol.23 (4), p.601-614
Main Authors: Aceto, Luca, Cassar, Ian, Francalanza, Adrian, Ingólfsdóttir, Anna
Format: Article
Language:English
Subjects:
Computer Science
Control systems
Enforcement
Safety
Software Engineering
Software Engineering/Programming and Operating Systems
Synthesis
Theory of Computation
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Summary:Runtime enforcement and control system synthesis are two verification techniques that automate the process of transforming an erroneous system into a valid one. As both techniques can modify the behaviour of a system to prevent erroneous executions, they are both ideal for ensuring safety. In this paper, we investigate the interplay between these two techniques and identify control system synthesis as being the static counterpart to suppression-based runtime enforcement, in the context of safety properties.
ISSN:1433-2779
1433-2787
DOI:10.1007/s10009-021-00624-0