Soft-core embedded FPGA based system on chip

Nowadays, there has been an intensive increase in embedded systems complexity. So that optimization and performance development become an interesting topic to study. In this proposal, the main problem to solve is to make the possibility to get more flexibility, to reduce cost and to improve performa...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2021-12, Vol.109 (3), p.517-533
Main Authors: Saidi, Hajer, Turki, Mariem, Marrakchi, Zied, Abid, Mohamed, Obeid, Abdulfattah
Format: Article
Language:English
Subjects:
Algorithms
Benchmarks
Circuits and Systems
Coders
Electrical Engineering
Embedded systems
Engineering
Error correction
Field programmable gate arrays
Hardware
Optimization
Performance enhancement
Reconfiguration
Run time (computers)
Signal,Image and Speech Processing
Software
System on chip
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Summary:Nowadays, there has been an intensive increase in embedded systems complexity. So that optimization and performance development become an interesting topic to study. In this proposal, the main problem to solve is to make the possibility to get more flexibility, to reduce cost and to improve performance. Considering this fact, we introduce in this paper a reconfigurable component integrated into Cortex M0 based System on Chip (SoC) which has the form of embedded FPGA. To the best of our knowledge, this is the first reconfigurable SoC composed of Tree-based embedded FPGA. Besides, we explored the different ways to reach the integration and the different steps. Then, we compared reconfigurable SoC with another developed SoC which contains many hardware accelerators which are a set of popular benchmarks in terms of performance and area. Finally, we take a popular error correction algorithm “RS-Encoder” as a test case. We made the profiling of this software application in order to compare the reconfigurable SoC with a classic SoC in terms of run-time. Preliminary results were presented and showed that the eFPGA integration introduces a chip area overhead but it proves interesting results in terms of run-time. Indeed, for 100 software instructions, the eFPGA is faster 4 times compared to a hardware accelerator and 412 times compared to the software implementation of the RS Encoder application.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-021-01872-5