A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in...

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Bibliographic Details
Published in:arXiv.org 2022-02
Main Authors: Sun, H, Sun, Q, Biereigel, S, Francisco, R, Gong, D, Huang, G, Huang, X, Kulis, S, Leroux, P, Liu, C, Liu, T, Moreira, P, Prinzie, J, J Wu, J Ye, Zhang, L, Zhang, W
Format: Article
Language:English
Subjects:
Calibration
Circuits
Clock generators
CMOS
Heavy ions
Linear energy transfer (LET)
Phase locked loops
Redundancy
Single event upsets
Vibration
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Summary:We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.
ISSN:2331-8422
DOI:10.48550/arxiv.2110.12625