Stable, Low Power and Bit-Interleaving Aware SRAM Memory for Multi-Core Processing Elements

• Published in: Electronics (Basel) 2021-11, Vol.10 (21), p.2724
• Main Authors: Yadav, Nandakishor, Kim, Youngbae, Li, Shuai, Choi, Kyuwon Ken
• Format: Article
• Language: English
• Subjects: Artificial neural networks; Circuits; Data processing; Deep learning; Hypotheses; Machine learning; Microprocessors; Parallel processing; Random access memory; Reliability; Stability; Static random access memory; Transistors
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics10212724

The machine learning and convolutional neural network (CNN)-based intelligent artificial accelerator needs significant parallel data processing from the cache memory. The separate read port is mostly used to design built-in computational memory (CRAM) to reduce the data processing bottleneck. This memory uses multi-port reading and writing operations, which reduces stability and reliability. In this paper, we proposed a self-adaptive 12T SRAM cell to increase the read stability for multi-port operation. The self-adaptive technique increases stability and reliability. We increased the read stability by refreshing the storing node in the read mode of operation. The proposed technique also prevents the bit-interleaving problem. Further, we offered a butterfly-inspired SRAM bank to increase the performance and reduce the power dissipation. The proposed SRAM saves 12% more total power than the state-of-the-art 12T SRAM cell-based SRAM. We improve the write performance by 28.15% compared with the state-of-the-art 12T SRAM design. The total area overhead of the proposed architecture compared to the conventional 6T SRAM cell-based SRAM is only 1.9 times larger than the 6T SRAM cell.