Eight-Level/Cell Storage by Tuning the Spatial Distribution of Dielectrics in a Tri-Layer ReRAM Cell: Electrical Characteristics and Reliability

Eight level resistance switching in a tri-layer ReRAM cell (ZrO x /AlO x /HfO x ) of fixed stack thickness was obtained by tuning the spatial location of its intermediate AlO x layer hence by varying its spatial distribution of three dielectrics. Here we have investigated the underlying reason behin...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on device and materials reliability 2021-12, Vol.21 (4), p.587-593
Main Authors: Vishwakarma, Kavita, Kishore, Rishabh, Datta, Arnab
Format: Magazinearticle
Language:English
Subjects:
Dielectrics
Electrical resistance measurement
Fatigue tests
Hafnium oxide
low power
Materials reliability
Metals
Multi-level
Resistance
resistance variability
Room temperature
Spatial distribution
stack optimization
Switches
Switching
Temperature measurement
tri-layer ReRAM
Tuning
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Eight level resistance switching in a tri-layer ReRAM cell (ZrO x /AlO x /HfO x ) of fixed stack thickness was obtained by tuning the spatial location of its intermediate AlO x layer hence by varying its spatial distribution of three dielectrics. Here we have investigated the underlying reason behind the observed well separated low power resistance switching in this type of valance change memory (VCM) cell achieved by varying its SET current compliance and discussed stack design aspect which impacts its characteristics. Electrical characteristics of a favorable cell obtained by our scheme demonstrate non-overlapped and retainable resistance levels even followed by dc endurance cycles. 10 6 SET/RESET cycle-based ac-endurance measurement was furthermore performed to assess resistance margin between the HRS and the LRS, and favorable cell exhibited well behaved cell-to-cell and cycle-to-cycle variabilities of its resistance states. Furthermore, retention measurements conducted at room temperature and at 85°C demonstrate stable non-overlapped resistance levels as suitable for the multi-level/cell storage. SET bias scaling of the favorable cell has been finally assessed by numerical simulation
ISSN:1530-4388
1558-2574
DOI:10.1109/TDMR.2021.3120966