An energy efficient multi-target binary translator for instruction and data level parallelism exploitation

Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as s...

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Bibliographic Details
Published in:Design automation for embedded systems 2022-03, Vol.26 (1), p.55-82
Main Authors: Knorst, Tiago, Vicenzi, Julio, Jordan, Michael G., Almeida, Jonathan H. de, Korol, Guilherme, Beck, Antonio C. S., Rutzig, Mateus B.
Format: Article
Language:English
Subjects:
Accelerators
CAE) and Design
Circuits and Systems
Computer-Aided Engineering (CAD
Electronic devices
Embedded systems
Energy conservation
Energy management systems
Engineering
Exploitation
Household appliances
Microprocessors
Neon
Performance enhancement
Special Purpose and Application-Based Systems
Study and teaching
Translators
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Summary:Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent engineering, which is not considered in current embedded processors. This work visited a set of embedded applications showing the need for concurrent ILP and DLP exploitation. For that, we propose a Hybrid Multi-Target Binary Translator (HMTBT) to transparently exploit ILP and DLP by using a CGRA and ARM NEON engine as targeted accelerators. Results show that HMTBT transparently achieves 24% performance improvements and 54% energy savings over an OoO superscalar processor coupled to an ARM NEON engine. The proposed approach improves performance and energy in 10%, 24% over decoupled binary translators using the same accelerator with the same ILP and DLP capabilities.
ISSN:0929-5585
1572-8080
DOI:10.1007/s10617-021-09258-6