An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2022-03, Vol.69 (3), p.844-848
Main Authors: Pereira-Rial, Oscar, Lopez, Paula, Carrillo, Juan M., Brea, Victor M., Cabello, Diego
Format: Article
Language:English
Subjects:
Adaptive biasing
analog integrated circuits
capacitor-less LDO
Circuit design
Circuit stability
Circuits
Logic gates
low-power
nano-ampere
Power consumption
Regulators
super source follower
Threshold voltage
Transient response
Transistors
Voltage measurement
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Summary:This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO's error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2021.3130674