Design of a High Speed Architecture of MQ-Coder for JPEG2000 on FPGA

Digital imaging is omnipresent today. In many areas, digitized images replace their analog ancestors such as photographs or X-rays. The world of multimedia makes extensive use of image transfer and storage. The volume of these files is very high and the need to develop compression algorithms to redu...

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Bibliographic Details
Published in:International journal of advanced computer science & applications 2017-01, Vol.8 (6)
Main Authors: Salem, Taoufik, Mahmoud, Hafedh
Format: Article
Language:English
Subjects:
Algorithms
Coders
Computer science
Decomposition
Digital imaging
Field programmable gate arrays
Hardware
High speed
Image compression
Information technology
Modules
Multimedia
Optimization
Probability
Quality standards
Real time
Time compression
Time lag
Video compression
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Summary:Digital imaging is omnipresent today. In many areas, digitized images replace their analog ancestors such as photographs or X-rays. The world of multimedia makes extensive use of image transfer and storage. The volume of these files is very high and the need to develop compression algorithms to reduce the size of these files has been felt. The JPEG committee has developed a new standard in image compression that now also has the status of Standard International: JPEG 2000. The main advantage of this new standard is its adaptability. Whatever the target application, whatever resources or available bandwidth, JPEG 2000 will adapt optimally. However, this flexibility has a price: the JPEG2000 perplexity is far superior to that of JPEG. This increased complexity can cause problems in applications with real-time constraints. In such cases, the use of a hardware implementation is necessary. In this context, the objective of this paper is the realization of a JPEG2000 encoder architecture satisfying real-time constraints. The proposed architecture will be implemented using programmable chips (FPGA) to ensure its effectiveness in real time. Optimization of renormalization module and byte-out module are described in this paper. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The design was implemented targeting a Xilinx Virtex 6 and an Altera Stratix FPGAs. Experimental results show that the proposed hardware architecture achieves real-time compression on video sequences on 35 fps at HDTV resolution.
ISSN:2158-107X
2156-5570
DOI:10.14569/IJACSA.2017.080621