A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array

Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capaci...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2022-05, Vol.69 (5), p.2433-2437
Main Authors: Ha, Sangwoo, Kim, Sangjin, Han, Donghyeon, Um, Soyeon, Yoo, Hoi-Jun
Format: Article
Language:English
Subjects:
Accuracy
Capacitors
Cell leakage-robust
Circuits
Computer architecture
Computer memory
computing-in-memory (CIM)
Density
Efficiency
embedded DRAM
Energy efficiency
error canceling
high SNR
Leakage
Microprocessors
Power consumption
Power management
PVT-robust
Robustness (mathematics)
Signal to noise ratio
Switches
Voltage
zero-gating
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Summary:Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capacity with a high density cell. Although the eDRAM-CIM has a higher density than the SRAM-CIM, it suffers from both poor robustness and a low signal-to-noise ratio (SNR). In this brief, the energy-efficient eDRAM-CIM macro is proposed while improving computational robustness and SNR with three key features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4% PVT variation reduction and 51.4% refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1%. According to these new features, the proposed eDRAM-CIM macro achieves 81.5-to-115.0 TOPS/W energy-efficiency with 209-to-295 \mu \text{W} power consumption when 4b \times 4b MAC operation is performed with 250 MHz core frequency. The proposed macro also achieves 91.52% accuracy at the CIFAR-10 object classification dataset (ResNet-20) without accuracy drop even with PVT variation.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2022.3159808