Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations

• Published in: Microprocessors and microsystems 2022-04, Vol.90, p.104498, Article 104498
• Main Authors: Arya, Neelam, Soni, Teena, Pattanaik, Manisha, Sharma, G.K.
• Format: Article
• Language: English
• Subjects: Accuracy-energy trade-off; Application specific integrated circuits; Approximate computing; Approximate divider; Arithmetic and logic units; ASIC; Codec; Computation; Dividers; Error-resilient applications; Field programmable gate arrays; FPGA; Image processing; Rounding; Subtraction
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2022.104498

The main focus of approximate dividers has been on ASIC-based designs. However, for emerging applications, there is a need to design approximate arithmetic units compatible with FPGA applications due to their inherent capabilities. A separate approximate design concept for ASIC and FPGA systems diminish the benefits of approximate computing techniques. This work proposes an energy-efficient and logarithmic-based approximate divider (LEAD), suitable for both ASIC and FPGA-based applications. LEAD is based on functional approximation of arithmetic divider by rounding the inputs to nearest powers of two and computing division using basic addition/subtraction operations and shifters. The proposed approximate design is error-configurable and can be used for both signed and unsigned integers. The results show that the proposed unsigned 16-bit approximate design accomplishes 70% energy-efficiency compared to an accurate array divider on ASIC platforms with minimal accuracy loss. For FPGA implementation, the design shows minimum area utilization and energy savings of around 50% as compared with Vivado divider IPs. A case study in the form of implementation of G.729A voice codec on FPGA and change detection for images is done to illustrate the benefits of the proposed approximate divider design.