Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-07, Vol.69 (7), p.2832-2844
• Main Authors: Xu, Rongjin, Ye, Dawei, Shi, C. -J. Richard
• Format: Article
• Language: English
• Subjects: Bang-bang control; binary phase detectors (BPDs); Clocks; Design parameters; digital phase-locked loop (DPLL); Frequency locking; Frequency-domain analysis; injection-locked clock multiplier (ILCM); Jitter; Mathematical models; Multipliers; multiplying delay-locked loop (MDLL); Noise prediction; Phase detectors; Phase noise; Quantization (signal); Time domain analysis; Transfer functions; Vibration
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2022.3161763

The analysis of injection-locked clock multipliers (ILCMs) using bang-bang phase detectors (BBPDs) is challenging due to the nonlinear BBPD and the multi-rate injected oscillator. This paper presents an explicit analysis of digital ILCMs using BBPDs and proposed an intuitive approach to optimizing parameters with given noise sources. A time-domain analysis in the single-clock domain is presented to solve the closed-form expression of jitter in the ILCM. The proposed approach exhibits good consistency with simulations, for various design parameters and noise cases. With the predicted input-referred jitter, the equivalent BBPD gain is resolved to derive the frequency-domain noise transfer functions in concise forms. To achieve the desired performance with given specifications, recommended design procedures are summarized based on the proposed analysis and verified by simulations.