Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation

To achieve faster design closure, there is a need to provide a design framework for the design of ReRAM-based DNN (deep neural network) accelerator at the early design stage. In this paper, we develop a high-level ReRAM-based DNN accelerator design framework. The proposed design framework has the fo...

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Bibliographic Details
Published in:Electronics (Basel) 2022-07, Vol.11 (13), p.2107
Main Authors: Kao, Hsu-Yu, Huang, Shih-Hsu, Cheng, Wei-Kai
Format: Article
Language:English
Subjects:
Accuracy
Artificial neural networks
Behavior
C plus plus
Circuit design
Circuits
Cost control
Design
Design analysis
Designers
Energy efficiency
Hardware
Leakage current
Machine learning
Model accuracy
Neural networks
Performance evaluation
Programming languages
Simulation
Software
Space exploration
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Summary:To achieve faster design closure, there is a need to provide a design framework for the design of ReRAM-based DNN (deep neural network) accelerator at the early design stage. In this paper, we develop a high-level ReRAM-based DNN accelerator design framework. The proposed design framework has the following three features. First, we consider ReRAM’s non-linear properties, including lognormal distribution, leakage current, IR drop, and sneak path. Thus, model accuracy and circuit performance can be accurately evaluated. Second, we use SystemC with TLM modeling method to build our virtual platform. To our knowledge, the proposed design framework is the first behavior-level ReRAM deep learning accelerator simulator that can simulate real hardware behavior. Third, the proposed design framework can evaluate not only model accuracy but also hardware cost. As a result, the proposed design framework can be used for behavior-level design space exploration. In the experiments, we have deployed different DNN models on the virtual platform. Circuit performance can be easily evaluated on the proposed design framework. Furthermore, experiment results also show that the noise effects are different in different ReRAM array architectures. Based on the proposed design framework, we can easily mitigate noise effects by tuning architecture parameters.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics11132107