Asymmetric Crosstalk Harness Signaling for Common Eigenmode Elimination

• Published in: IEEE transactions on computers 2022-09, Vol.71 (9), p.2048-2058
• Main Authors: Iparraguirre, Daniel, Delgado-Frias, Jose G., Heck, Howard
• Format: Article
• Language: English
• Subjects: 3D routing; Arrays; Asymmetry; Binary data; CHS; common-mode; Couplings; Crosstalk; Decoding; Encoding; high-speed interface; multi-stripline stackup; Routing; Sensitivity; signal integrity; Signaling; source-synchronous transmission; Wires
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2021.3120242

This paper presents a novel scheme based on the Crosstalk Harnessed Signaling (CHS) technique for parallel high-speed interfaces. The proposed scheme, called Asymmetric Crosstalk Harnessed Signaling (ACHS), provides a robust and consistent eye opening for all the transmitted bits in the interface. The Hadamard matrix employed for CHS encoding has been modified to a non-square format in order to either eliminate the common eigenmode or turn it differential. This in turn results in a signaling scheme that converts a binary data array to a slightly larger signal/interconnect array. The resulting signaling and routing overhead translates into a comparable eye opening across all the bits inside the encoded bus, overcoming the crosstalk sensitivity associated to the common mode present in the original CHS scheme. Both CHS and the proposed ACHS are implemented on a 16-bit source-synchronous bus wired through 3-dimensional interconnect arrangements in a multi-stripline stackup, in order to compare performances in very aggressive crosstalk environments. Simulation results show a consistent eye opening across all data bits when ACHS is applied, rendering a fully functional bus with only 11% routing overhead, against a practically inoperable bus in the CHS case, due to the eye collapse for the common-mode encoded bit.