A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design

Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is deve...

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Bibliographic Details
Published in:Electronics (Basel) 2022-08, Vol.11 (15), p.2465
Main Authors: Park, Jung-Jin, Kang, Young-Min, Kim, Geon-Hak, Chang, Ik-Joon, Kim, Jinsang
Format: Article
Language:English
Subjects:
Current sources
Energy dissipation
Feedback
Latches
Layouts
Nodes
Propagation
Radiation
Radiation hardening
Single event upsets
Transistors
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Summary:Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics11152465