A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2022-09, Vol.30 (9), p.1269-1280
• Main Authors: Park, Youngmin, Jeon, Dongsuk
• Format: Article
• Language: English
• Subjects: Applications programs; Calibration; Capacitors; Charge pump (CP); Charge pumps; Clock generators; Clocks; Compensators; Current efficiency; Data preprocessing; Electric potential; Figure of merit; low-dropout regulator (LDO); Mobile computing; output-capacitor-free LDO; Regulators; Slew rate; Transient analysis; Transient response; Transistors; Voltage; Voltage control; voltage difference to time converter; voltage regulator
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2022.3180774

This article proposes a fully integrated output-capacitor-free low-dropout regulator (LDO) for mobile applications. To overcome the limited output voltage range of typical analog LDOs, our design uses a rail-to-rail voltage-difference-to-time-converter (VDTC) and a charge pump (CP) to achieve a wide output range. Using a self-calibrating clock generator (SCCG) removes the need for an external clock source and adaptively tunes the clock frequency, enabling fast transient responses while minimizing quiescent current. A tunable undershoot compensator (TUC) mitigates voltage droop by detecting the drop in the output voltage due to a sharp increase in load current and compensating the output voltage immediately. The proposed LDO is fabricated in a 65-nm low power (LP) CMOS process and demonstrates a maximum load current capacity of 270 mA. The input and output voltage ranges of the LDO are 0.5-1.2 and 0.15-1.15 V, respectively, with 12.7- \mu \text{A} quiescent current and 99.99% peak current efficiency. The measured undershoot and settling time are 150 mV and 100 ns at a slew rate of 200 mA/3 ns, respectively, achieving a figure of merit (FoM) of 0.183 fs.