Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits

• Published in: IEEE transactions on electron devices 2022-11, Vol.69 (11), p.6065-6071
• Main Authors: Lee, Kyu-Ho, Kwon, Dongseok, Woo, Sung Yun, Ko, Jong Hyun, Choi, Woo Young, Park, Byung-Gook, Lee, Jong-Ho
• Format: Article
• Language: English
• Subjects: AND-type array; Artificial neural networks; Biological neural networks; charge-trap flash (CTF); Current mirrors; integrate-and-fire (IF) neuron; Logic gates; MOSFET circuits; neuromorphic; Neurons; spike processing block (SPB); spiking neural networks (SNNs); Synapses; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2022.3207707

In this article, a highly linear spike processing block (SPB) integrating AND-type charge-trap flash (CTF) synapse array ( 25\times4 synapses) and CMOS integrate-and-fire (IF) neurons is fabricated for hardware-based spiking neural networks (SNNs). We investigate the synaptic behavior of the CTF cells and the operating principle of the neuron circuits. Under the given operating conditions, the fabricated SPB consistently exhibits a highly linear relationship ( {R}^{{2}} > 0.999) between the current sum and the output spike frequency, enabling the SNNs to precisely mimic the layer of artificial neural networks (ANNs) with rectified linear unit (ReLU) activation function. Based on the fabricated SPB, a single-layer SNN is experimentally demonstrated for classifying the 5\times5 digit patterns.