High-Efficiency Millimeter-Wave CMOS Oscillator Design Using Port Voltage/Current Optimization and T-Embedding Networks

We present an optimization-based design methodology for high-power and high-efficiency millimeter-wave fundamental oscillators in CMOS. The optimization is formulated to take into account the loss of the passive components to result in an optimal circuit design. Compared with previous methods, the p...

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Bibliographic Details
Published in:IEEE transactions on terahertz science and technology 2022-11, Vol.12 (6), p.550-564
Main Authors: Wang, Hao, Chen, Jingjun, Zhang, Li, Liu, Xiaoguang
Format: Article
Language:English
Subjects:
Circuit design
CMOS
Comparative studies
Complimentary metal-oxide semiconductor (CMOS)
Design optimization
Efficiency
Embedding
Logic gates
millimeter wave (mmW)
Millimeter waves
Optimization
Optimized production technology
oscillator
Oscillators
Passive components
Power amplifiers
Power generation
signal generator
submillimeter wave
Terahertz (THz)
transformer
Voltage
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Summary:We present an optimization-based design methodology for high-power and high-efficiency millimeter-wave fundamental oscillators in CMOS. The optimization is formulated to take into account the loss of the passive components to result in an optimal circuit design. Compared with previous methods, the proposed approach can produce the final design in a single pass of optimization with a fast and robust convergence profile. In this article, we also present a comparative study between the T- and the \Pi-embedding networks and show that T-embedding is superior to \Pi-embedding in terms of flexibility in biasing and sensitivity to component Q. As such, we argue that our design approach can target high output power and high efficiency separately to result in an optimal design for a given application. A design example of a 215-GHz fundamental oscillator in a 65-nm CMOS technology is presented to demonstrate the effectiveness of the proposed design approach. The oscillator achieves 5.17-dBm peak output power at 1.2-V supply with a corresponding dc-to-RF efficiency 12.3% and a peak efficiency of 13.7%. The measured phase noises are -90.0 and -116.2 dBc/Hz at 1 and 10 MHz offset, respectively. A second design example at 310 GHz also demonstrates state-of-the-art performance with a peak output power of -4 dBm and dc-to-RF efficiency of 3.2%.
ISSN:2156-342X
2156-3446
DOI:10.1109/TTHZ.2022.3186438