Software Design of VerilogHDL Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time of PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed...

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Bibliographic Details
Published in:Wireless personal communications 2023, Vol.128 (2), p.1087-1115
Main Authors: Dhanabalan, G., Selvi, S. Tamil
Format: Article
Language:English
Subjects:
Communications Engineering
Computer Communication Networks
Data acquisition
Engineering
Field programmable gate arrays
Ladder diagrams
Networks
Programmable logic arrays
Programmable logic controllers
Signal,Image and Speech Processing
Traffic control
Traffic signals
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Summary:Powerful advantages of programmable logic controller (PLC) dominate process industries. Scan time of PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. PLC programmers are not familiar with FPGA programming. But, FPGA does not support LD based programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement which helps simultaneous execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.
ISSN:0929-6212
1572-834X
DOI:10.1007/s11277-022-09990-7