Ka-Band Three-Stack CMOS Power Amplifier with Split Layout of External Gate Capacitor for 5G Applications

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize powe...

Full description

Saved in:
Bibliographic Details
Published in:Electronics (Basel) 2023-01, Vol.12 (2), p.432
Main Authors: Yang, Junhyuk, Lee, Jaeyong, Jang, Seongjin, Jeong, Hayeon, Park, Changkun
Format: Article
Language:English
Subjects:
Capacitors
Circuits
CMOS
Design
Driver stages
Efficiency
Extremely high frequencies
Layouts
Power amplifiers
Power consumption
Power semiconductor devices
Transistors
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this study, we designed a Ka-band two-stage differential power amplifier (PA) using a 65 nm RFCMOS process. To enhance the output power of the PA, a three-stack structure was utilized in the power stage, while the driver stage of the PA was designed with a common-source structure to minimize power consumption in the driver stage. The layout of an external gate capacitor for the stacked power stage was split to maximize the performance of the power transistor. With the proposed split layout of the external capacitor, gain, output power, and power-added efficiency (PAE) were improved. Additionally, a capacitive neutralization technique was applied to the power and driver stages to ensure the stability and enhance the gain of the PA. The measured P1dB and the saturation power were 22.0 dBm and 23.3 dBm, respectively, while the peak PAE was 27.8% at 28.5 GHz.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics12020432