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Post‐deposition annealing and interfacial atomic layer deposition buffer layers of Sb2Se3/CdS stacks for reduced interface recombination and increased open‐circuit voltages
Currently, Sb2Se3 thin films receive considerable research interest as a solar cell absorber material. When completed into a device stack, the major bottleneck for further device improvement is the open‐circuit voltage, which is the focus of the work presented here. Polycrystalline thin‐film Sb2Se3...
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Published in: | Progress in photovoltaics 2023-03, Vol.31 (3), p.203-219 |
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Main Authors: | , , , , , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Online Access: | Get full text |
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Summary: | Currently, Sb2Se3 thin films receive considerable research interest as a solar cell absorber material. When completed into a device stack, the major bottleneck for further device improvement is the open‐circuit voltage, which is the focus of the work presented here. Polycrystalline thin‐film Sb2Se3 absorbers and solar cells are prepared in substrate configuration and the dominant recombination path is studied using photoluminescence spectroscopy and temperature‐dependent current–voltage characteristics. It is found that a post‐deposition annealing after the CdS buffer layer deposition can effectively remove interface recombination since the activation energy of the dominant recombination path becomes equal to the bandgap of the Sb2Se3 absorber. The increased activation energy is accompanied by an increased photoluminescence yield, that is, reduced non‐radiative recombination. Finished Sb2Se3 solar cell devices reach open‐circuit voltages as high as 485 mV. Contrarily, the short‐circuit current density of these devices is limiting the efficiency after the post‐deposition annealing. It is shown that atomic layer‐deposited intermediate buffer layers such as TiO2 or Sb2S3 can pave the way for overcoming this limitation.
Substrate Sb2Se3/CdS‐based solar cells are fabricated with open‐circuit voltages as high as 485 mV. Interface recombination is reduced by a post‐deposition annealing after CdS buffer layer deposition, which directly impacts the open‐circuit voltage. Alternatively, ultrathin interfacial ALD buffer layers between the Sb2Se3 absorber and the CdS buffer layer are employed for increased open‐circuit voltages. |
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ISSN: | 1062-7995 1099-159X |
DOI: | 10.1002/pip.3625 |