Enabling Energy-Efficient In-Memory Computing with Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) b...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal on emerging and selected topics in circuits and systems 2023-03, Vol.13 (1), p.1-1
Main Authors: Kavitha, S, Vishvakarma, S. K., Reniwal, B. S.
Format: Article
Language:English
Subjects:
Arithmetic
Assist device
Bandwidth
Circuits
Computation
Computer architecture
Decoding
Digital Boolean logic
Feasibility
In memory computing
Random access memory
Reconfiguration
Sense amplifier
Sense amplifiers
Static random access memory
Transistors
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA [14], CSRAM [15], RRCSA [16] and the ADSA [17] respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.
ISSN:2156-3357
2156-3365
DOI:10.1109/JETCAS.2023.3243192