Layout of MOS Varactor with Improved Quality Factor for Cross-Coupled Differential Voltage-Controlled Oscillator Applications

• Published in: Electronics (Basel) 2023-03, Vol.12 (6), p.1385
• Main Authors: Lee, Milim, Lee, Jaeyong, Park, Changkun
• Format: Article
• Language: English
• Subjects: Layouts; Parasitics (electronics); Q factors; Silicon substrates; Simulation; Varactor diodes; Voltage controlled oscillators; Wireless communications
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics12061385

In this study, we designed an MOS varactor for application in the differential voltage-controlled oscillator (VCO). To improve the quality factor of the MOS varactor, we proposed a symmetric layout technique of the MOS varactor with reduced parasitic components. Compared with the typical MOS varactor layout, the metal line for the interconnection of the MOS varactors that is inevitable in the typical MOS varactors for the cross-coupled VCO was minimized to reduce the parasitic resistance. In addition, with the reduced interconnection metal line, the overall size of the proposed MOS varactor was also reduced compared with the typical one. To verify the feasibility of the proposed MOS varactor structure, the typical and proposed MOS varactors were designed using a 180 nm RFCMOS process. Compared to the typical MOS varactor, the measured quality factor of the proposed MOS varactor was improved by approximately 32% at the operating frequency of 5.0 GHz. Additionally, we successfully verified that the parasitic capacitance induced by the lossy silicon substrate was reduced in the proposed MOS varactor structure.