Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

• Published in: Electronics (Basel) 2023-04, Vol.12 (8), p.1891
• Main Authors: Nam, Jae-Hyeon, Park, Sung-Hyun, Jang, Jin-Yeop, Park, Sang-Gyu
• Format: Article
• Language: English
• Subjects: Arrays; Capacitors; Circuit design; Design and construction; Digital-to-analog converters; Efficiency; Energy consumption; Errors; Linearity; Methods; Power consumption; Power management; Switching; Switching circuits
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics12081891

Capacitive DACs (C-DACs) are widely used as stand-alone DACs or in an ADC as auxiliary DACs. An important performance metric of a C-DAC is its energy consumption and the linearity between the digital input and the analog output. In multi-bit C-DACs, the mismatch between the capacitors can degrade linearity, which can be important in high-resolution applications. In this work, we analyze the power consumption and linearity performance of a class of C-DACs called split-array C-DACs. We show that the simple element rotation technique, which is widely used to suppress the mismatch error of DACs, cannot be used with the power-efficient three-level switching scheme to effectively suppress the mismatch error. Then, we propose a switching scheme which can be used with the power efficient three-level switching and can suppress the in-band mismatch error effectively.