Dual-Band 802.11ax Transceiver Design With 1024-QAM and 160-MHz CBW Support

A [Formula Omitted]ax transceiver design is presented to support dual-band simultaneous operation (DBS) and 1024-QAM modulation. The proposed architecture features linearity enhancement for uplink orthogonal frequency division multiple access (OFDMA) and wideband transmission. With integrated low-ph...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2023, Vol.6, p.137-140
Main Authors: Lu, Chao, Chen, Shr-Lung, Liu, Jun, Bao, Jian, Wang, Yufei, Zhao, Yi
Format: Article
Language:English
Subjects:
Frequency division multiple access
Narrowband
Noise generation
Orthogonal Frequency Division Multiplexing
Phase locked loops
Phase noise
Quadrature amplitude modulation
Receiving
Sensitivity
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Summary:A [Formula Omitted]ax transceiver design is presented to support dual-band simultaneous operation (DBS) and 1024-QAM modulation. The proposed architecture features linearity enhancement for uplink orthogonal frequency division multiple access (OFDMA) and wideband transmission. With integrated low-phase noise clock generation and phase locked loop (PLL), best-in-class receiving sensitivity and lowest transmission EVM floor are demonstrated through measurements. With 20-MHz (HE20) receiving, −96.5/−66 dBm sensitivity level is measured for MSC0/11, respectively. The output power reaches 18 dBm with −35-dB EVM for 80 MHz 1024-QAM (HE80 MCS11) transmission at 5-GHz band. Narrowband OFDMA signals can be transmitted at full power capacity, and 160-MHz channel bandwidth (CBW) can also be supported without digital predistortion (DPD). The fully integrated transceiver occupies 10.5-mm2 silicon area in 22-nm CMOS.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2023.3268136