Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning

This letter presents a scalable technique to reduce the power of the analog input stage in neural recording front-ends in Globalfoundries 22 -nm FDSOI. The back-gate voltages are adapted to reduce the threshold voltage and thus allow supply voltage reduction. This adaption increases PVT stability of...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2023, Vol.6, p.145-148
Main Authors: Schüffny, Franz Marcus, Höppner, Sebastian, Hänzsche, Stefan, George, Richard Miru, Zeinolabedin, Seyed Mohammad Ali, Mayr, Christian
Format: Article
Language:English
Subjects:
Modulators
Power consumption
Recording
Threshold voltage
Voltage reduction
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Summary:This letter presents a scalable technique to reduce the power of the analog input stage in neural recording front-ends in Globalfoundries 22 -nm FDSOI. The back-gate voltages are adapted to reduce the threshold voltage and thus allow supply voltage reduction. This adaption increases PVT stability of subthreshold circuits. A comparison to a conventional delta–sigma ADC is drawn and the minimum power point is measured, resulting in 0.7 -[Formula Omitted]/channel at 7.2 -[Formula Omitted] input-referred noise. Additionally, the transition to smaller technologies promises low-power consumption in the digital domain, by allowing smaller supply voltage and higher integration density.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2023.3270243