Generate Compilers from Hardware Models

Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already...

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Bibliographic Details
Published in:arXiv.org 2023-05
Main Authors: Smith, Gus Henry, Kushigian, Ben, Canumalla, Vishal, Cheung, Andrew, Just, René, Tatlock, Zachary
Format: Article
Language:English
Subjects:
Compilers
Hardware
Synthesis
Online Access:Get full text
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Summary:Compiler backends should be automatically generated from hardware design language (HDL) models of the hardware they target. Generating compiler components directly from HDL can provide stronger correctness guarantees, ease development effort, and encourage hardware exploration. Past work has already championed this idea; here we argue that advances in program synthesis make the approach more feasible. We present a concrete example by demonstrating how FPGA technology mappers can be automatically generated from SystemVerilog models of an FPGA's primitives using program synthesis.
ISSN:2331-8422