Design of high-speed data access between shared virtual memories in network on chip

In wormhole routing, each packet having unstable number of flits the messages where it is prepared as multiplepackets. The packet target information is hold by the header flits. Virtual Channels (VCs) are used by each port which results the efficient data flow and to share a physical communication c...

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Bibliographic Details
Main Authors: Jabez, J., Ajitha, P., Sivasangari, A., Jinila, Y. Bevish, Gowri, S., Srinivasulu, Senduru
Format: Conference Proceeding
Language:English
Subjects:
Frequency synthesizers
System on chip
Wormhole routeing
Online Access:Get full text
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Summary:In wormhole routing, each packet having unstable number of flits the messages where it is prepared as multiplepackets. The packet target information is hold by the header flits. Virtual Channels (VCs) are used by each port which results the efficient data flow and to share a physical communication channel between the by many packets in NoC systems. In this proposed work also focuses on the design of High Speed Data Access between all Shared Virtual Memories in Network on Chip (NoC). Here, Globally Asynchronous Locally Synchronous (GSAS) move toward is beginto development multi core functions and we execute frequency synthesizer to sustain various frequencies. Finally, Power, Delay and Cell Utilization were calculated from the proposed method. Experimental results are shown in Xilinx ISE 13.1i software.
ISSN:0094-243X
1551-7616
DOI:10.1063/5.0142854