High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator

The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using AI in power-limited applications. In this paper...

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Bibliographic Details
Published in:IEEE transactions on emerging topics in computing 2023-04, Vol.11 (2), p.527-533
Main Authors: Nasab, Milad Tanavardi, Amirany, Abdolah, Moaiyeri, Mohammad Hossein, Jafari, Kian
Format: Article
Language:English
Subjects:
Artificial intelligence
Artificial neural networks
binarized neural network
Carbon nanotubes
Circuit design
Circuits
CNTFETs
Convolutional neural networks
Data transmission
Delays
Energy dissipation
Field effect transistors
GAA-CNTFET
Hardware
hardware accelerator
Logic gates
logic-in-memory
Magnetic tunneling
Neural networks
Power consumption
Power management
Semiconductor devices
Spintronic
Transistors
Tunnel junctions
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Summary:The convolutional neural network (CNN) is a significant part of the artificial intelligence (AI) systems widely used in different tasks. The binarized neural networks (BNNs) reduce power consumption and hardware overhead to answer the demands for using AI in power-limited applications. In this paper, a BNN hardware accelerator is proposed. The proposed approach is based on a novel nonvolatile XNOR/XOR circuit designed using the magnetic tunnel junction (MTJ) and gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) devices. The nonvolatility of the proposed design leads to the elimination of external memory access that significantly decreases the data transmission delay and power dissipation. Moreover, it consumes low energy, which is very critical in battery-operated devices. Furthermore, the combinational read circuitry of the proposed design leads to high robustness to process variations. According to the simulation results, our proposed design has a logical error rate of 0.0164%, which is negligible and offers a significantly high network accuracy even in the presence of significant process variations. Our proposed hardware accelerator provides at least 13%, 29%, and 41% improvements regarding power, power delay product (PDP), and area compared to its state-of-the-art counterparts.
ISSN:2168-6750
2168-6750
DOI:10.1109/TETC.2022.3202113