Configurable and High-Throughput CIM SRAM for Boolean Logic Operation With 321 GOPS/kb and 164395.6 GOPS/mm2

In this letter, we propose a twin-operand computing method based on transforming a static random-access memory (SRAM) macro that can be used for image processing. The proposed cross-coupled 10T cell structure can be configured into a dual 4T structure, and the computational results can be stored in...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2023, Vol.6, p.153-156
Main Authors: Lin, Zhiting, Jin, Qian, Tong, Zhongzhen, Li, Guangdong, Gu, Shuo, Li, Jingzheng, Wang, Ruixuan, Shu, Xinglong, Yu, Shuiyue, Yan, Shengyuan, Liu, Li, Hao, Licai, Zhao, Qiang, Peng, Chunyu, Wu, Xiulong
Format: Article
Language:English
Subjects:
Computer architecture
Computing-in-memory (CIM)
Image processing
in situ storage
logic operation
Memory management
Microprocessors
Random access memory
Static random access memory
static random-access memory (SRAM)
Throughput
Transistors
twin-operand
von Neumann bottleneck
Writing
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Summary:In this letter, we propose a twin-operand computing method based on transforming a static random-access memory (SRAM) macro that can be used for image processing. The proposed cross-coupled 10T cell structure can be configured into a dual 4T structure, and the computational results can be stored in situ, thus significantly improving energy efficiency. Furthermore, unlike previous designs, the proposed computation-in-memory (CIM) macro allows independent operands, where two operands are stored in dual 4T. Not only can it provide computational functions but it can also double the storage density. The measurement results of a 55-nm CMOS prototype chip show that it achieves the highest throughput of 321 GOPS/kb, 164395.6 GOPS/mm 2 , and 364.2 TOPS/W at 1.2 V.
ISSN:2573-9603
DOI:10.1109/LSSC.2023.3281587