Towards On-Board SAR Processing with FPGA Accelerators and a PCIe Interface

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the R...

Full description

Saved in:
Bibliographic Details
Published in:Electronics (Basel) 2023-06, Vol.12 (12), p.2558
Main Authors: Baungarten-Leon, Emilio Isaac, Martín-del-Campo-Becerra, Gustavo Daniel, Ortega-Cisneros, Susana, Schlemon, Maron, Rivera, Jorge, Reigber, Andreas
Format: Article
Language:English
Subjects:
Accelerators
Algorithms
Bandwidths
Bus interconnections
Central processing units
Computer interfaces
CPUs
Data processing
Design and construction
Digital integrated circuits
Digital signal processors
Efficiency
Fast Fourier transformations
Field programmable gate arrays
Ground stations
High level languages
High level synthesis
IP (Internet Protocol)
Pipelining (computers)
Power
Programming languages
Routines
Synthetic aperture radar
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics12122558