FPGA-based fast carry predict adder

Delay owing to the addition logic plays a vital role in numerous digital applications. This delay linearly increases with the bit-size. Fast two operand addition using Carry Predict Adder (CPrA) with reduced critical path delay is proposed in this paper. Theoretical delay analysis of CPrA shows 96.9...

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Bibliographic Details
Main Author: Nesame, J. Jean Jenifer
Format: Conference Proceeding
Language:English
Subjects:
Adding circuits
Delay
Reduction
Online Access:Get full text
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Summary:Delay owing to the addition logic plays a vital role in numerous digital applications. This delay linearly increases with the bit-size. Fast two operand addition using Carry Predict Adder (CPrA) with reduced critical path delay is proposed in this paper. Theoretical delay analysis of CPrA shows 96.97% delay reduction compared to conventional carry propagation adder for 32-bit two operand addition. The verification of CPrA on FPGA-Xilinx Virtex-5 family shows 54.03% delay reduction compared to fast hybrid adder design.
ISSN:0094-243X
1551-7616
DOI:10.1063/5.0118610