Low-Complexity FPGA Implementation of 106.24Gbps DP-QPSK Coherent Optical Receiver With Fractional Oversampling Rate Based on One FIR Filter for Resampling, Retiming and Equalizing

A novel low-complexity combined resampling, retiming and equalizing (RRE) algorithm is proposed. The RRE algorithm uses a single FIR filter for resampling, retiming and equalizing and thus lower the complexity. In the numerical simulation, with an oversampling rate of 32/27, compared to the traditio...

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Bibliographic Details
Published in:Journal of lightwave technology 2023-08, Vol.41 (16), p.5244-5251
Main Authors: Song, Jingwei, Li, Yan, Qiu, Jifang, Hong, Xiaobin, Guo, Hongxiang, Yang, Zhisheng, Wu, Jian
Format: Article
Language:English
Subjects:
Algorithms
Clock recovery
Coherence
coherent optical communication
Complexity
Complexity theory
digital signal processing
Equalizers
field programmable gate array
Finite impulse response filters
FIR filters
Frequency domain analysis
Interpolation
Optical receivers
Oversampling
Resampling
Signal processing algorithms
Symbols
Time domain analysis
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Summary:A novel low-complexity combined resampling, retiming and equalizing (RRE) algorithm is proposed. The RRE algorithm uses a single FIR filter for resampling, retiming and equalizing and thus lower the complexity. In the numerical simulation, with an oversampling rate of 32/27, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the error vector magnitude (EVM) by 0.036 dB and 0.043 dB and the complexity is lowered by 48.3% and 31.9%, respectively. In the offline experiment, with a received optical power of -35 dBm, compared to the traditional time-domain scheme with a 15-tap CMA equalizer and the frequency-domain scheme based on 256-point FFT, the RRE algorithm with a 15-tap RRE filter lowers the EVM by 0.26 dB and 0.36 dB. And the RRE algorithm respectively lowers the complexity by 48.3% and 31.9%. The RRE algorithm also enables a real-time 106.24 Gbps (26.56 GBaud) DP-QPSK coherent optical receiver based on a single FPGA chip using four 6-bit ADCs with a sampling rate of ∼31.48 GSa/s. The FPGA-based receiver achieves a sensitivity of -34 dBm at BER of 1E-3. As far as we know, this is the highest reported bit rate of a coherent receiver based on a single FPGA chip.
ISSN:0733-8724
1558-2213
DOI:10.1109/JLT.2023.3258072