3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

• Published in: IEEE journal of the Electron Devices Society 2023-01, Vol.11, p.1-1
• Main Authors: Lin, Yi-Wen, Lin, Shan-Wen, Chen, Bo-An, Sun, Chong-Jhe, Yan, Siao-Cheng, Luo, Guang-Li, Wu, Yung-Chun, Hou, Fu-Ju
• Format: Article
• Language: English
• Subjects: complementary FET (CFET); Fabrication; Field effect transistors; Ge nanowire (NW); Germanium; Logic gates; Metals; Nanowires; Performance evaluation; Self alignment; Self-aligned; Semiconductor devices; Semiconductor process modeling; Si FinFET; Silicon; single gate; Xself-aligned
• ISSN: 2168-6734; 2168-6734
• DOI: 10.1109/JEDS.2023.3309812

In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of 166 A/m at VD = VG-VTH = -0.5 V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of 3.03 × 105, 3.4 × 104 at VD = -0.05 V and -0.5 V, respectively. The Si nFinFET presents an ION of 60.4 A/m at VD = VG-VTH = 0.5 V and shows SSmin of 91, 101 mV/dec, and ION/IOFF of 9.01 × 104, 5.62 × 105 at VD = 0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node.