Smart pixel sensors: towards on-sensor filtering of pixel clusters with deep learning

Highly granular pixel detectors allow for increasingly precise measurements of charged particle tracks. Next-generation detectors require that pixel sizes will be further reduced, leading to unprecedented data rates exceeding those foreseen at the High Luminosity Large Hadron Collider. Signal proces...

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Bibliographic Details
Published in:arXiv.org 2023-10
Main Authors: Yoo, Jieun, Dickinson, Jennet, Swartz, Morris, Giuseppe Di Guglielmo, Bean, Alice, Berry, Douglas, Manuel Blanco Valentin, DiPetrillo, Karri, Fahim, Farah, Gray, Lindsey, Hirschauer, James, Kulkarni, Shruti R, Lipton, Ron, Maksimovic, Petar, Mills, Corrinne, Neubauer, Mark S, Parpillon, Benjamin, Pradhan, Gauri, Syal, Chinar, Tran, Nhan, Wen, Dahai, Young, Aaron
Format: Article
Language:English
Subjects:
Charged particles
Circuit design
Clusters
Data reduction
Detectors
Integrated circuits
Large Hadron Collider
Luminosity
Machine learning
Neural networks
Particle tracking
Physical properties
Pixels
Smart sensors
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Summary:Highly granular pixel detectors allow for increasingly precise measurements of charged particle tracks. Next-generation detectors require that pixel sizes will be further reduced, leading to unprecedented data rates exceeding those foreseen at the High Luminosity Large Hadron Collider. Signal processing that handles data incoming at a rate of O(40MHz) and intelligently reduces the data within the pixelated region of the detector at rate will enhance physics performance at high luminosity and enable physics analyses that are not currently possible. Using the shape of charge clusters deposited in an array of small pixels, the physical properties of the traversing particle can be extracted with locally customized neural networks. In this first demonstration, we present a neural network that can be embedded into the on-sensor readout and filter out hits from low momentum tracks, reducing the detector's data volume by 54.4-75.4%. The network is designed and simulated as a custom readout integrated circuit with 28 nm CMOS technology and is expected to operate at less than 300 \(\mu W\) with an area of less than 0.2 mm\(^2\). The temporal development of charge clusters is investigated to demonstrate possible future performance gains, and there is also a discussion of future algorithmic and technological improvements that could enhance efficiency, data reduction, and power per area.
ISSN:2331-8422