A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with ret...

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Bibliographic Details
Published in:arXiv.org 2023-10
Main Authors: Bauer, Heiner, Stolba, Marco, Scholze, Stefan, Walter, Dennis, Mayr, Christian, Oefelein, Alexander, Höppner, Sebastian, Scharfe, André, Schraut, Flo, Eisenreich, Holger
Format: Article
Language:English
Subjects:
High temperature
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Summary:We present a low-power, energy efficient 32-bit RISC-V microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures, by using an adaptive reverse body biasing aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from -40 {\deg}C to 125 {\deg}C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.
ISSN:2331-8422
DOI:10.48550/arxiv.2310.09094